1. Field of the Invention
Embodiments relate to a delay locked loop (DLL) circuit, a semiconductor device employing a DLL circuit and a method of controlling a DLL circuit. In particular, embodiments relate to a DLL circuit configured to generate multi-phase clock signals, a semiconductor device employing the DLL circuit and a method of controlling the DLL circuit.
2. Description of the Related Art
In general, a delay locked loop (DLL) circuit may be employed in a semiconductor integrated circuit so as to generate an internal clock signal. Typically, in a DLL circuit, an internal clock signal is generated by delaying a system clock signal or an external clock signal by a predetermined delay time. The DLL circuit detects phases of an internal clock signal and an external clock signal, and controls a delay time by a shift operation so as to synchronize the internal clock signal with the external clock signal.
In a semiconductor memory device, such as a dynamic random access memory (DRAM), an internal clock signal generated by a DLL circuit is employed as a timing signal for operating the semiconductor memory device. For example, in a semiconductor memory device, an internal clock signal may be used as a clock signal to output data from the semiconductor memory device and to store data in the semiconductor memory device.
Generally, when memory cells are activated or when memory cells are accessed during a read mode, additional current from an internal supply voltage may be required. The change in demand of current from the internal supply voltage may change a voltage provided to a DLL circuit. The change of the voltage provided to the DLL circuit may change a delay quantity applied to an external clock signal, and as a result the external clock signal may be not synchronized with an internal clock signal. When the external clock signal is not synchronized with the internal clock signal, the DLL circuit may perform a shift operation to compensate for the decrease in the internal supply voltage. Therefore, the external clock signal may be synchronized with the internal clock signal by the DLL circuit.
A DLL circuit employing a coarse loop and a fine loop may be used to lock clock signals of a semiconductor integrated circuit. However, a DLL circuit such as this may not be configured to lock clock signals of a semiconductor integrated circuit that may employ multi-phase clock signals.
Accordingly, there remains a need for a DLL circuit that may address one or more of these concerns.